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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21369-1E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F78UL
s DESCRIPTION
The Fujitsu MB15F78UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2600 MHz and a 1200 MHz prescalers. A 32/33 or a 64/65 for the 2600 MHz prescaler, and a 16/17 or a 32/33 for the 1200 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 4.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The data format is the same as the previous one MB15F08SL, MB15F78SP Fast locking . is achieved for adopting the new circuit. The new package (BCC20) decreases a mount area of MB15F78UL more than 30% comparing with the former BCC16 (for dual PLL) . MB15F78UL is ideally suited for wireless mobile communications, such as GSM and PCS.
s FEATURES
: RX synthesizer : 2600 MHz Max. : TX synthesizer : 1200 MHz Max. * Low power supply voltage : VCC = 2.4 to 3.6 V * Ultra low power supply current : ICC = 4.5 mA Typ. (VCC = Vp = 2.7 V, Ta = +25 C, SWTX = SWRX = 0, in TX/RX locking state) (Continued) * High frequency operation
s PACKAGES
20-pin plastic TSSOP 20-pad plastic BCC
(FPT-20P-M06)
(LCC-20P-M05)
MB15F78UL
(Continued) * Direct power saving function : Power supply current in power saving mode Typ. 0.1 A (VCC = Vp = 2.7 V, Ta = +25C) Max. 10 A (VCC = Vp = 2.7 V) * Software selectable charge pump current : 1.5 mA/6.0 mA Typ. * Dual modulus prescaler : 2600 MHz prescaler (32/33 or 64/65) /1200 MHz prescaler (16/17 or 32/33) * 23-bit shift register * Serial input binary 14-bit programmable reference divider : R = 3 to 16,383 * Serial input programmable divider consisting of : - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter : 3 to 2,047 * Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit * On-chip phase control for phase comparator * On-chip phase comparator for fast lock and low noise * Built-in digital locking detector circuit to detect PLL locking and unlocking * Operating temperature : Ta = -40 to +85 C * Serial data format compatible with MB15F08SL
s PIN ASSIGNMENTS
(TSSOP-20) TOP VIEW
OSCIN GND finTX XfinTX GNDTX VCCTX PSTX VpTX DoTX LD/fout 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Clock Data LE finRX XfinRX GNDRX VCCRX PSRX VpRX DoRX finTX XfinTX GNDTX VCCTX PSTX VpTX 1 2 3 4 5 6 7 8 9 10
(BCC-20) TOP VIEW
OSCIN Data GND Clock 20 19 18 17 16 15 14 13 12 11 LE finRX XfinRX GNDRX VCCRX PSRX
DoRX DoTX LD/fout VpRX
(FPT-20P-M06)
(LCC-20P-M05)
2
MB15F78UL
s PIN DESCRIPTION
Pin no. TSSOP 1 2 3 4 5 6 BCC 19 20 1 2 3 4 Pin name I/O OSCIN GND finTX XfinTX GNDTX VCCTX I Descriptions The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor. Prescaler input pin for the TX-PLL. Connection to an external VCO should be via AC coupling. Prescaler complimentary input pin for the TX-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the TX-PLL section (except for the charge pump circuit) , the oscillator input buffer and the shift register. Power saving mode control pin for the TX-PLL section. This pin must be set at "L" when the power supply is started up. (Open is prohibited.) PSTX = "H" ; Normal mode/PSTX = "L" ; Power saving mode Charge pump output pin for the TX-PLL section. Lock detect signal output (LD) /phase comparator monitoring output (fout) .The output signal is selected by LDS bit in the serial data. LDS bit = "H" ; outputs fout signal/LDS bit = "L" ; outputs LD signal Charge pump output pin for the RX-PLL section. Power saving mode control pin for the RX-PLL section. This pin must be set at "L" when the power supply is started up. (Open is prohibited.) PSRX = "H" ; Normal mode/PSRX = "L" ; Power saving mode Power supply voltage input pin for the RX-PLL section (except for the charge pump circuit) Prescaler complimentary input pin for the RX-PLL section. This pin should be grounded via a capacitor. Prescaler input pin for the RX-PLL. Connection to an external VCO should be via AC coupling. Load enable signal input pin (with the schmitt trigger circuit) When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (TX-ref. counter, TX-prog. counter, RX-ref.counter, RX-prog.counter) according to the control bit in a serial data. Clock input pin for the 23-bit shift register (with a schmitt trigger circuit) One bit of data is shifted into the shift register on a rising edge of the clock.
Ground pin for OSC input buffer and the shift register circuit. I I
Ground pin for the TX-PLL section. I
7 8 9 10 11 12 13
5 6 7 8 9 10 11
PSTX VpTX DOTX LD/fout DORX VpRX PSRX
Power supply voltage input pin for the TX-PLL charge pump. O O O
Power supply voltage input pin for the RX-PLL charge pump. I
14 15 16 17
12 13 14 15
VCCRX GNDRX XfinRX finRX
Ground pin for the RX-PLL section I I
18
16
LE
I
19
17
Data
I
20
18
Clock
I
3
MB15F78UL
s BLOCK DIAGRAM
VCCTX GNDTX 6 (4) 5 (3) VpTX 8 (6)
Fast lock Tuning
PSTX 7 (5)
Intermittent mode control (TX-PLL)
3 bit latch LDS SWTX FCTX
7 bit latch
Binary 7-bit swallow counter TX-PLL)
11 bit latch
Binary 11-bit programmable counter (TX-PLL)
Phase comp. (TX-PLL)
Charge Current pump Switch 9 DoTX (TX-PLL) (7)
(1) finTX 3 XfinTX 4 (2)
Prescaler (TX-PLL) (16/17, 32/33) 2 bit latch T1 T2 14 bit latch Binary 14-bit programmable ref. counter(TX-PLL) frTX 1 bit latch
fpTX
Lock Det. (TX-PLL) LDTX
C/P setting counter
Fast lock Tuning LD/fout LD frTX frRX fpTX fpRX
C/P setting counter
OSCIN 1 (19)
AND
10 LD/ (8) fout
OR frRX T1 (15) finRX 17 XfinRX 16 (14)
Prescaler (RX-PLL) (32/33, 64/65) Binary 14-bit programmable ref. counter (RF-PLL)
T2
2 bit latch
LDRX 14 bit latch 1 bit latch fpRX Lock Det. (RX-PLL)
Fast lock Tuning
PSRX 13 (11)
Intermittent mode control (RX-PLL)
LDS SWRX FCRX 3 bit latch
Binary 7-bit swallow counter (RX-PLL)
Binary 11-bit programmable counter (RX-PLL)
7 bit latch
11 bit latch
Phase comp. (RX-PLL)
Charge pump Current (RX-PLL) Switch
11 DoRX (9)
LE 18 (16) (17) Data 19 Clock 20 (18)
Schmitt circuit
Latch selector
Schmitt circuit Schmitt circuit
CC N N 23-bit shift register 12
2 (20) GND
14 (12) 15 (13) VCCRX GNDRX
12 (10) VpRX
O : TSSOP ( ) : BCC 4
MB15F78UL
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature
LD/fout DoTX, DoRX
Symbol VCC Vp VI VO VDD Tstg
Rating Min. -0.5 VCC -0.5 GND GND -55 Max. 4.0 4.0 VCC + 0.5 VCC Vp +125
Unit V V V V V C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC Vp VI Ta Value Min. 2.4 VCC GND -40 Typ. 2.7 2.7 Max. 3.6 3.6 VCC +85 Unit V V V C Remarks VCCRX = VCCTX
Note : * VCCRX, VpRX, VCCTX and VpTX must supply equal voltage. Even if either RX-PLL or TX-PLL is not used, power must be supplied to VCCRX, VpRX, VCCTX and VpTX to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. * Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the following precautions when handling the device. * When storing and transporting the device, put it in a conductive case. * Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. Use a conductive sheet on working bench. * Before fitting the device into or removing it from the socket, turn the power supply off. * When handling (such as transporting) the device mounted board, protect the leads with a conductive sheet. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15F78UL
s ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = -40 C to +85 C) Parameter Symbol ICCTX *1 Power supply current ICCRX *1 Power saving current finTX *3 Operating frequency finRX * finTX Input sensitivity finRX OSCIN
"H" level input voltage
3
Condition finTX = 910 MHz VCCTX = VpTX = 2.7 V finRX = 2500 MHz VCCRX = VpRX = 2.7 V PSTX = PSRX = "L" PSTX = PSRX = "L" TX PLL RX PLL
Value Min. 1.1 1.8 100 400 3 -15 -15 0.5 0.7 VCC + 0.4 0.7 VCC -1.0 -1.0 0 -100 VCC - 0.4 Vp - 0.4 1.0 Typ. 1.7 2.8 0.1 *2 0.1 *2 Max. 2.4 3.9 10 10 1200 2600 40 +2 +2 VCC 0.3 VCC - 0.4 0.3 VCC +1.0 +1.0 +100 0 0.4 0.4 2.5 -1.0
Unit mA mA A A MHz MHz MHz dBm dBm VP - P V V V V A A A A V V V V nA mA mA
IPSTX IPSRX finTX finRX fOSC PfinTX PfinRX VOSC VIH VIL VIH VIL IIH *4 IIL *4 IIH IIL *4 VOH VOL DoTX DoRX DoTX DoRX LD/fout VDOH VDOL IOFF IOH *4 IOL
OSCIN
TX PLL, 50 system RX PLL, 50 system
"L" level input voltage
"H" level input voltage
Data, LE, Clock PSTX PSRX Data LE Clock PSTX PSRX OSCIN
Schmitt trigger input Schmitt trigger input

"L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current "H" level output voltage "L" level output voltage "H" level output voltage "L" level output voltage High impedance cutoff current "H" level output current "L" level output current
LD/fout
VCC = Vp = 2.7 V, IOH = -1 mA VCC = Vp = 2.7 V, IOL = 1 mA VCC = Vp = 2.7 V, IDOH = -0.5 mA VCC = Vp = 2.7 V, IDOL = 0.5 mA VCC = Vp = 2.7 V VOFF = 0.5 V to Vp - 0.5 V VCC = Vp = 2.7 V VCC = Vp = 2.7 V
(Continued)
6
MB15F78UL
(Continued)
(VCC = 2.4 V to 3.6 V, Ta = -40 C to +85 C) Symbol DoTX *8 DoRX DoTX *8 DoRX IDOL/IDOH Charge pump current rate vs VDO vs Ta Condition VCC = Vp = 2.7 V, CS bit = "H" VDOH = Vp / 2, CS bit = "L" Ta = +25 C VCC = Vp = 2.7 V, CS bit = "H" VDOL = Vp / 2, CS bit = "L" Ta = +25 C VDO = Vp / 2 0.5 V VDO Vp - 0.5 V -40 C Ta +85 C, VDO = Vp / 2 Value Min. -8.2 -2.2 4.1 0.8 Typ. -6.0 -1.5 6.0 1.5 3 10 5 Max. -4.1 -0.8 8.2 2.2 Unit mA mA mA mA % % %
Parameter
"H" level output current
IDOH *4
"L" level output current
IDOL IDOMT *5 IDOVD *
6
IDOTA *7
*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 C, SW = "L" in locking state. *2 : VCCTX = VpTX = VCCRX = VpRX = 2.7 V, fosc = 12.8 MHz, Ta = +25 C, in power saving mode. PSTX = PSRX = GND VIH = VCC, VIL = GND (at CLK, Data, LE) *3 : AC coupling. 1000 pF capacitor is connected under the condition of Min. operating frequency. *4 : The symbol "-" (minus) means the direction of current flow. *5 : VCC = Vp = 2.7 V, Ta = +25 C (||I3| - |I4||) / [ (|I3| + |I4|) / 2] x 100 (%) *6 : VCC = Vp = 2.7 V, Ta = +25 C [ (||I2| - |I1||) / 2] / [ (|I1| + |I2|) / 2] x 100 (%) (Applied to both lDOL and lDOH) *7 : VCC = Vp = 2.7 V, [||IDO (+85 C) | - |IDO (-40 C) || / 2] / [|IDO (+85 C) | + |IDO (-40 C) | / 2] x 100 (%) (Applied to both IDOL and IDOH) *8 : When Charge pump current is measured, set LDS = "L" , T1 = "L" and T2 = "H".
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 Vp/2 Vp - 0.5 Vp
Charge pump output voltage (V)
7
MB15F78UL
s FUNCTIONAL DESCRIPTION
1. Pulse swallow function
fVCO = [ (P x N) + A] x fOSC / R fVCO : Output frequency of external voltage controlled oscillator (VCO) P : Preset divide ratio of dual modulus prescaler (16 or 32 for TX-PLL, 32 or 64 for RX-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127, A < N) fOSC : Reference oscillation frequency (OSCIN input frequency) R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RXPLL sections, programmable reference dividers of TX/RX-PLL sections are controlled individually. The serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. The programmable reference counter for the TX-PLL CN1 CN2 0 0 The programmable reference counter for the RX-PL 1 0 The programmable counter and the swallow counter for the TX-PLL 0 1 The programmable counter and the swallow counter for the RX-PLL 1 1
(1) Shift Register Configuration
* Programmable Reference Counter
(LSB) Data Flow (MSB)
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
16
17
18
19 20 21 22 23 X X X
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
CS : Charge pump current select bit R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383) T1, 2 : LD/fout output setting bit CN1, 2 : Control bit X : Dummy bits (Set "0" or "1") Note : Data input with MSB first.
8
MB15F78UL
* Programmable Counter
(LSB) Data Flow (MSB)
1
2
3
4 SW
TX/RX
5 FC
TX/RX
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
22
23
CN1 CN2 LDS
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
A1 to A7 LDS SWTX/RX FCTX/RX CN1, 2
: Divide ratio setting bits for the swallow counter (0 to 127) : LD/fout signal select bit : Divide ratio setting bit for the prescaler (TX : SWTX, RX : SWRX) : Phase control bit for the phase detector (TX : FCTX, RX : FCRX) : Control bit
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
Note : Data input with MSB first. (2) Data setting * Binary 14-bit Programmable Reference Counter Data Setting Divide ratio 3 4 * * * 16383 R14 0 0 * * * 1 R13 0 0 * * * 1 R12 0 0 * * * 1 R11 0 0 * * * 1 R10 0 0 * * * 1 R9 0 0 * * * 1 R8 0 0 * * * 1 R7 0 0 * * * 1 R6 0 0 * * * 1 R5 0 0 * * * 1 R4 0 0 * * * 1 R3 0 1 * * * 1 R2 1 0 * * * 1 R1 1 0 * * * 1
Note : Divide ratio less than 3 is prohibited. * Binary 11-bit Programmable Counter Data Setting Divide ratio 3 4 * * * 2047 N11 0 0 * * * 1 N10 0 0 * * * 1 N9 0 0 * * * 1 N8 0 0 * * * 1 N7 0 0 * * * 1 N6 0 0 * * * 1 N5 0 0 * * * 1 N4 0 0 * * * 1 N3 0 1 * * * 1 N2 1 0 * * * 1 N1 1 0 * * * 1
Note : Divide ratio less than 3 is prohibited. * Binary 7-bit Swallow Counter Data Setting Divide ratio A7 A6 A5 A4 A3 A2 A1 0 1 * * * 127 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 1 * * * 1
9
MB15F78UL
* Prescaler Data Setting Divide ratio Prescaler divide ratio TX-PLL Prescaler divide ratio RX-PLL * Charge Pump Current Setting Current value CS 6.0 mA 1.5 mA 1
0
SW = "H" 16/17 32/33
SW = "L" 32/33 64/65
* LD/fout output Selectable Bit Setting LD/fout pin state LD output frTX fout output frRX fpTX fpRX LDS 0 0 0 1 1 1 1 T1 0 1 1 0 1 0 1 T2 0 0 1 0 0 1 1
* Phase Comparator Phase Switching Data Setting Phase comparator input fr > fp fr < fp fr = fp Z : High-impedance FC = "H" DoTX/DoRX H L Z FC = "L" DoTX/DoRX L H Z
Depending upon the VCO and LPF polarity, FC bit should be set.
High
(1)
(1) VCO polarity FC = "H" (2) VCO polarity FC = "L"
VCO Output Frequency
(2) LPF Output voltage Max.
Note : Give attention to the polarity for using active type LPF.
10
MB15F78UL
3. Power Saving Mode (Intermittent Mode Control Circut)
Status Normal mode Power saving mode PSTX/PSRX pins H L
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pins high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes : * When power (VCC) is first applied, the device must be in standby mode, PSTX = PSRX = Low, for at least 1 s. * PS pins must be set at "L" at Power-ON
OFF VCC Clock Data LE PSTX PSRX (1) tV 1 s
ON
tPS 100 ns
(2)
(3)
(1) PSTX = PSRX = "L" (power saving mode) at Power-ON (2) Set serial data at least 1 s after the power supply becomes stable (VCC 2.2 V) . (3) Release power saving mode (PSTX, PSRX : "L" "H") at least 100 ns after setting serial data.
11
MB15F78UL
4. Serial data input timing
Divide ratio setting is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing.
1st data 2nd data
Control bit
Invalid data
Data
MSB
LSB
Clock
t1 t7 t2 t3 t6
LE
t4 t5
Parameter t1 t2 t3 t4
Min. 20 20 30 30
Typ.
Max.
Unit ns ns ns ns
Parameter t5 t6 t7
Min. 100 20 100
Typ.
Max.
Unit ns ns ns
Note : LE should be "L" when the data is transferred into the shift register.
12
MB15F78UL
s PHASE COMPARATOR OUTPUT WAVEFORM
frTX/ frRX
fpTX/ fpRX
tWU tWL
LD
(FC bit = High) DoTX/ DoRX H Z L (FC bit = Low) DoTX/ DoRX H Z L
LD Output Logic Table TX-PLL section Locking state/Power saving state Locking state/Power saving state Unlocking state Unlocking state
RX-PLL section Locking state/Power saving state Unlocking state Locking state/Power saving state Unlocking state
LD output H L L L
Notes : * Phase error detection range = -2 to +2 * Pulses on DoTX/DoRX signals are output to prevent dead zone. * LD output becomes low when phase error is tWU or more. * LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCIN input frequency as follows. tWU 2/fosc : e.g. tWU 156.3 ns when fosc = 12.8 MHz tWU 4/fosc : e.g. tWL 312.5 ns when fosc = 12.8 MHz
13
MB15F78UL
s TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout Oscilloscope 1000 pF VpTX 0.1 F VCCTX 0.1 F 1000 pF 50 S.G.
1000 pF LD/ fout 10 S.G.
DoTX 9
VpTX 8
PSTX 7
VCCTX 6
GNDTX 5
XfinTX 4
finTX 3
GND 2
OSCIN 1
50
11 DoRX
12 VpRX
13 PSRX
14 VCCRX
15 GNDRX
16 XfinRX
17 finRX
18 LE
19 Data
20 Clock
1000 pF
Controller (devide ratio setting)
1000 pF VpRX 0.1 F 0.1 F VCCRX 50 S.G.
Note : The terminal number shows that of TSSOP-20
14
MB15F78UL
s TYPICAL CHARACTERISTICS
1. fin input sensitivity
RX-PLL input sensitivity vs. Input frequency
10 0
PfinRX (dBm)
-10 -20 -30 -40 -50 0 400 800 1200
SPEC
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC 1600 2000 2400 2800 3200 3600 4000
finRX (MHz)
TX-PLL input sensitivity vs. Input frequency
10 0 -10 -20 -30 -40 -50 0 200 400 600 800 1000 1200 1400 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC SPEC
PfinTX (dBm)
finTX (MHz)
15
MB15F78UL
2. OSCIN input sensitivity
Input sensitivity vs. Input frequency
10 SPEC
Input sensitivity VOSC (dBm)
0 -10 -20 -30 -40 -50 -60 VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC 0 50 100 150 200 250 300
Input frequency fOSC (MHz)
16
MB15F78UL
3. Do output current (RX PLL)
* 1.5 mA mode IDO - VDO
10.0
Charge pump output current IDO (mA)
VCC = Vp = 2.7 V
0
-10.0 0.0 1.0 2.0 3.0
Charge pump output voltage VDO (V)
* 6.0 mA mode
IDO - VDO
10.0
Charge pump output current IDO (mA)
VCC = Vp = 2.7 V
0
-10.0 0.0 1.0 2.0 3.0
Charge pump output voltage VDO (V)
17
MB15F78UL
4. Do output current (TX PLL)
* 1.5 mA mode IDO - VDO
10.0
Charge pump output current IDO (mA)
VCC = Vp = 2.7 V
0
-10.0 0.0 1.0 2.0 3.0
Charge pump output voltage VDO (V)
* 6.0 mA mode IDO - VDO
10.0
Charge pump output current IDO (mA)
VCC = Vp = 2.7 V
0
-10.0 0.0 1.0 2.0 3.0
Charge pump output voltage VDO (V)
18
MB15F78UL
5. fin input impedance
finTX input impedance
4 : 9.6016 -68.832 1.9269 pF 1 200.000 000 MHz 1 : 317.09 -831.5 100 MHz 2 : 30.898 -233.42 400 MHz 3 : 13.227 -112.79 800 MHz
1
2
4
3
START 100.000 000 MHz
STOP 1 200.000 000 MHz
finRX input impedance
4 : 12.588 -3.4751 17.615 pF 2 600.000 000 MHz 1 : 43.75 -235.95 400 MHz 2 : 12.82 -88.188 1 GHz 3 : 9.7227 -25.9 2 GHz
4
1
3 2
START 400.000 000 MHz
STOP 2 600.000 000 MHz
19
MB15F78UL
6. OSCIN input impedance
OSCIN input impedance
4 : 28.844 -691.13 2.3028 pF
100.000 000 MHz 1 : 12.953 k -13.003 k 3 MHz 2 : 478.13 -3.4268 k 20 MHz 3 : 118.19 -1.7321 k 40 MHz
4
1 2 3
START 3.000 000 MHz
STOP 100.000 000 MHz
20
MB15F78UL
s REFERENCE INFORMATION (for Look-up time, Phase noise and Reference leakage)
Test Circuit S.G. OSCIN DO fin Spectrum Analyzer LPF
fVCO = 2490 MHz KV = 52 MHz/V fr = 200 kHz fOSC = 19.8 MHz LPF
VCC = 3.0 V VVCO = 2.5 V Ta = +25 C CP : 1.5 mA mode
24 k
VCO
82 pF
15 k 820 pF
22 pF
* PLL Reference Leakage
ATTEN 10 dB RL 0 dBm VAVG 39 10 dB/ MKR -67.50 dB 200 kHz
MKR D 200 kHz S -67.50 dB
CENTER 2.490008 GHz RBW 3.0 kHz VBW 3.0 kHz
SPAN 1.000 MHz SWP 280 ms
* PLL Phase Noise
ATTEN 10 dB RL 0 dBm VAVG 48 10 dB/ MKR -59.33 dB 1.00 kHz
MKR D 1.00 kHz S -59.33 dB
CENTER 2.49000640 GHz RBW 100 Hz VBW 100 Hz
SPAN 10.00 kHz SWP 802 ms
(Continued)
21
MB15F78UL
(Continued)
* PLL Lock-up time 2.49 GHz2.55 GHz within 1 kHz LchHch 222 s * PLL Lock-up time 2.55 GHz2.49 GHz within 1 kHz HchLch 267 s
2.550011500 GHz
2.490011500 GHz
2.550007500 GHz
2.490007500 GHz
2.550003500 GHz -1.911 ms T1 400 s 3.089 ms 1.000 ms/div T2 622 s 8.089 ms 222 s
2.490003500 GHz -1.911 ms T1 422 s 3.089 ms 1.000 ms/div T2 689 s 8.089 ms 267 s
22
MB15F78UL
s APPLICATION EXAMPLE
OUTPUT from controller 1000 pF VCO 2.7 V 1000 pF 0.1 F LPF 2.7 V
0.1 F
Clock 20
Data 19
LE 18
finRX 17
XfinRX 16
GNDRX 15
VCCRX 14
PSRX 13
VpRX 12
DoRX 11
MB15F78UL 1 OSCIN 2 GND 3 finTX 4 XfinTX 5 GNDTX 6 VCCTX 7 PSTX 8 VpTX 9 DoTX 10 LD/fout
Lock Det. 1000 pF 1000 pF 1000 pF 2.7 V 2.7 V
0.1 F TCXO OUTPUT VCO
0.1 F
LPF
Notes : *Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up register to prevent oscillation when open-circuit in the input) . *The terminal number shows that of TSSOP-20.
23
MB15F78UL
s USAGE PRECAUTIONS
(1) VCCRX, VpRX, VCCTX and VpTX must be equal voltage. Even if either RX-PLL or TX-PLL is not used, power must be supplied to VCCRX, VpRX, VCCTX and VpTX to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions : -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting or removing this device into or from a socket. -Protect leads with conductive sheet, when transporting a board mounted device.
s ORDERING INFORMATION
Part number MB15F78ULPFT MB15F78ULPVA Package 20-pin, plastic TSSOP (FPT-20P-M06) 20-pad, plastic BCC (LCC-20P-M05) Remarks
24
MB15F78UL
s PACKAGE DIMENSIONS
20-pin plastic TSSOP (FPT-20P-M06)
* 6.500.10(.256.004)
20 11
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness.
0.170.05 (.007.002)
* 4.400.10
INDEX
6.400.20 (.173.004) (.252.008)
Details of "A" part 1.050.05 (Mounting height) (.041.002) LEAD No.
1 10
0.65(.026)
"A" 0.240.08 (.009.003) 0.13(.005)
M
0~8
+0.03 +.001
(0.50(.020)) 0.45/0.75 (.018/.030)
0.07 -0.07 .003 -.003 (Stand off) 0.25(.010)
0.10(.004)
C
1999 FUJITSU LIMITED F20026S-2C-2
Dimensions in mm (inches)
(Continued)
25
MB15F78UL
(Continued) 20-pad plastic BCC (LCC-20P-M05)
3.00(.118)TYP 3.600.10(.142.004)
16 11
0.550.05 (.022.002) (Mounting height)
11
0.250.10 (.010.004)
16
0.250.10 (.010.004) INDEX AREA 3.400.10 (.134.004) 2.70(.106) TYP "D" "A" "B" "C"
0.50(.020) TYP
1
6
6
1
0.0750.025 (.003.001) (Stand off)
0.50(.020) TYP 2.80(.110)REF
0.05(.002)
Details of "A" part 0.500.10 (.020.004)
Details of "B" part 0.500.10 (.020.004)
Details of "C" part 0.500.10 (.020.004) C0.20(.008)
Details of "D" part 0.300.10 (.012.004)
0.600.10 (.024.004)
0.300.10 (.012.004)
0.600.10 (.024.004)
0.400.10 (.016.004)
C
2001 FUJITSU LIMITED C20056S-c-2-1
Dimensions in mm (inches)
26
MB15F78UL
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0106 (c) FUJITSU LIMITED Printed in Japan

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